library verilog;
use verilog.vl_types.all;
entity uart_baud_generate is
    generic(
        baud_115200_cycle: integer := 7;
        baud_19200_cycle: integer := 41;
        baud_9600_cycle : integer := 81;
        baud_cycle_num  : vl_notype
    );
    port(
        sys_clk_i       : in     vl_logic;
        rst_n_baud      : in     vl_logic;
        baud_clk_o      : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of baud_115200_cycle : constant is 1;
    attribute mti_svvh_generic_type of baud_19200_cycle : constant is 1;
    attribute mti_svvh_generic_type of baud_9600_cycle : constant is 1;
    attribute mti_svvh_generic_type of baud_cycle_num : constant is 3;
end uart_baud_generate;
